Quite a bit of progress, at least up the learning curve, leading to the electronic equivalent of the ubiquitous "Hello World!" program, flashing LEDs.
A number of obstacles learning opportunities encountered along the way. The first was that, although the CPU operated OK in the ModelSim simulator, optimisation during the actual synthesis step was a little too good and resulted in zero logic elements being used. In other words, a blank FPGA!
After much head scratching I deferred to the great brains on AlteraForum. To cut a long story short, the program that was currently hard coded into the CPU's VHDL model did not include any commands that would drive any of the chips pins. The synthesiser had determined that the CPU was having no effect on the outside world, and so optimised all the internal logic into nothingness!
A very helpful Altera GURU, rbughalo, set me straight, and provided some very useful direction. The upshot is that the model now uses one of Altera's pre-defined ROM types, and that in turn is initialised from a separate data file. The net result is that the synthesiser can't know which opcodes will be used or not, and so can't "optimise" any of it out of existence.
Of course, that resulted in a number of other changes...