v 0.4 of my CPU is a decent delta. The code is now cleaner, more generic and so more flexible and easy to expand. The internal structure has expanded to include a new flag, zero ("Z"), to go with the existing numerical overflow flag ("OV"). Most importantly, these in turn facilitate conditional branching. Yes Sir, we can loopy! Follow the "Read More" link at the right for an explanation of the new instructions. | 24/02/2013 |
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AuthorJust another hobbyist starting out with FPGAs. Archives
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